Fix AArch64 encodings for by element instructions.
authorTamar Christina <tamar.christina@arm.com>
Fri, 29 Jun 2018 11:12:27 +0000 (12:12 +0100)
committerTamar Christina <tamar.christina@arm.com>
Fri, 29 Jun 2018 11:14:42 +0000 (12:14 +0100)
commit369c9167d47e69aad2e260cc1db17f8c894c138b
tree62ede76b5bebce22e14c81c2c74fa036b82cc63a
parentfd1ae9058720aa2738cc4852647097dd89c2bb88
Fix AArch64 encodings for by element instructions.

Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.

e.g. fmla restricts Rm to 4 bits when using an FP16 register.  This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.

Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.

This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).

Also the patch updates all instructions that should be affected by this.

opcodes/

PR binutils/23192
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
* aarch64-opc.c (operand_general_constraint_met_p,
aarch64_print_operand): Likewise.
* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
fmlal2, fmlsl2.
(AARCH64_OPERANDS): Add Em2.

gas/

PR binutils/23192
* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
AARCH64_OPND_Em16
* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
16 registers.
* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.

include/

PR binutils/23192
*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
16 files changed:
gas/ChangeLog
gas/config/tc-aarch64.c
gas/testsuite/gas/aarch64/advsimd-armv8_3.d
gas/testsuite/gas/aarch64/advsimd-armv8_3.s
gas/testsuite/gas/aarch64/advsimd-compnum.d
gas/testsuite/gas/aarch64/advsimd-compnum.s
gas/testsuite/gas/aarch64/sve.d
include/ChangeLog
include/opcode/aarch64.h
opcodes/ChangeLog
opcodes/aarch64-asm-2.c
opcodes/aarch64-dis-2.c
opcodes/aarch64-dis.c
opcodes/aarch64-opc-2.c
opcodes/aarch64-opc.c
opcodes/aarch64-tbl.h