drm/i915/gen9: Add 2us read latency to WM level
authorVandana Kannan <vandana.kannan@intel.com>
Tue, 4 Nov 2014 17:06:46 +0000 (17:06 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 7 Nov 2014 17:42:06 +0000 (18:42 +0100)
commit367294be7c257dd4d8d8f0e296aa9824eae18568
tree2c8e2963c69f4e7992f5016713820d3f8faf26db
parent3078999f2a4ee4aaabf9df2166e4e43581bb357a
drm/i915/gen9: Add 2us read latency to WM level

According to the updated Bspec, The mailbox response data is not currently
accounting for memory read latency. Add 2 microseconds to the result for
each level.
This patch adds 2us to latency of level 0 for all cases and
for all other levels (1-7) only if latency[level] > 0.

v2: Slightly rework the patch and add a big comment (Damien)
v3: Rebase on top of the renames of the memory latency defines

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v1)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Reviewed-by: M, Satheeshakrishna <satheeshakrishna.m@intel.com> (v1)
Cc: Lespiau, Damien <damien.lespiau@intel.com>
Cc: M, Satheeshakrishna <satheeshakrishna.m@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c