gpio: Add Aspeed driver
authorJoel Stanley <joel@jms.id.au>
Tue, 30 Aug 2016 07:54:27 +0000 (17:24 +0930)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 7 Sep 2016 14:56:47 +0000 (16:56 +0200)
commit361b79119a4b7f53f728913b5ed2c8d2d10c16f5
treebb31d4df905d64d1973d3ab9a97bd3ee73d6abc7
parent19de85134ee92d927044cc620961a322bfde9119
gpio: Add Aspeed driver

The Aspeed SoCs contain GPIOs banked by letter, where each bank contains
8 pins. The GPIO banks are then grouped in sets of four in the register
layout.

The implementation exposes multiple banks through the one driver and
requests and releases pins via the pinctrl subsystem. The hardware
supports generation of interrupts from all GPIO-capable pins.

A number of hardware features are not yet supported: Configuration of
interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance
for output ports.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/gpio-aspeed.c [new file with mode: 0644]