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(parent: 1eb4f3d) | patch
[MIPS] Fix register renaming in the interrupt handlers.
authorrts <rts@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 18 Aug 2015 12:42:12 +0000 (12:42 +0000)
committerrts <rts@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 18 Aug 2015 12:42:12 +0000 (12:42 +0000)
commit35ed5ce385e923a872f1371f1e4793508ca140f1
tree086a2c0a88767149b195b4a2fb6395acd370962ctree | snapshot
parent1eb4f3d294214e972cda083fafac5045228a3a29commit | diff
[MIPS] Fix register renaming in the interrupt handlers.

gcc/
* config/mips/mips-protos.h (mips_hard_regno_rename_ok): New prototype.
* config/mips/mips.c (mips_hard_regno_rename_ok): New function.
(mips_hard_regno_scratch_ok): Likewise.
(TARGET_HARD_REGNO_SCRATCH_OK): Define macro.
* config/mips/mips.h (HARD_REGNO_RENAME_OK): New.

gcc/testsuite/
* gcc.target/mips/interrupt_handler-bug-1.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226968 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog diff | blob | history
gcc/config/mips/mips-protos.h diff | blob | history
gcc/config/mips/mips.c diff | blob | history
gcc/config/mips/mips.h diff | blob | history
gcc/testsuite/ChangeLog diff | blob | history
gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c [new file with mode: 0644] blob
Domain: System / Toolchain;