i2c: designware: Calculate SCL timing parameter for High Speed Mode
authorWan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Tue, 7 Apr 2020 13:34:39 +0000 (21:34 +0800)
committerWolfram Sang <wsa@the-dreams.de>
Wed, 15 Apr 2020 11:13:39 +0000 (13:13 +0200)
commit35eba185fd1a3c61556a3050edbddc58d953303f
tree8a9384dda5d9f930ec0106dc1fba8c0433ab9dc9
parent85f8fcaeed33315e19905af23f2693a81956688a
i2c: designware: Calculate SCL timing parameter for High Speed Mode

Custom parameters for HCNT/LCNT are not available for OF based system.
Thus, we will use existing SCL timing parameter calculation functions
for High Speed Mode too.

The value for the parameters tSYMBOL and tLOW is taken from DesignWare
DW_apb_i2c Databook v2.01a, section 3.15.4.6. The calculation should
assume higher bus load since it gives slower timing parameter.

Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
drivers/i2c/busses/i2c-designware-master.c