haswell: use at least 64 URB entries for GT2+.
authorGwenole Beauchesne <gwenole.beauchesne@intel.com>
Mon, 7 May 2012 06:54:56 +0000 (08:54 +0200)
committerXiang, Haihao <haihao.xiang@intel.com>
Tue, 23 Oct 2012 05:50:28 +0000 (13:50 +0800)
commit35db124a6bdbccd02db2b54ae2072f33830e65fa
tree4735b5b98d08c271c74b2ae12fbfcfbb75c3310b
parent43b9fb68f12657f1f7afa6be101355f92e36ede1
haswell: use at least 64 URB entries for GT2+.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
src/i965_render.c