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(parent: 300d95c) | patch
clk: renesas: r9a07g044: Add M3 Clock support
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 30 Apr 2022 11:41:53 +0000 (12:41 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 May 2022 10:10:21 +0000 (12:10 +0200)
commit359f10c1b02d3c65c7eba6146e5b7962f0abbd93
tree3f759078febf6f33f94c1ab687d7d6b1a3b954abtree | snapshot
parent300d95c5bbb4cb59a149e436ed162a0ca09cdca1commit | diff
clk: renesas: r9a07g044: Add M3 Clock support

Add support for M3 clock which is sourced from DSI divider connected
to PLL5_4 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
Domain: System / Kernel;