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(parent: cf63e9d) | patch
[AArch64] Perform last active true vector combine
authorzhongyunde <zhongyunde@huawei.com>
Mon, 14 Mar 2022 17:19:39 +0000 (01:19 +0800)
committerzhongyunde <zhongyunde@huawei.com>
Mon, 14 Mar 2022 17:25:03 +0000 (01:25 +0800)
commit3568333815b30dc565ce041c64e871bc1d4e8e21
tree84fc9e64ca32c5ddf5932ce5b9fe23ba9ce5dfe6tree | snapshot
parentcf63e9d4caccbd540df083c63a5217ac50b5e1f9commit | diff
[AArch64] Perform last active true vector combine

Test bit of lane EC-1 can use P register directly, eg:
Materialize : Idx = (add (mul vscale, NumEls), -1)
               i1 = extract_vector_elt t37, Constant:i64<Idx>
    ... into: "ptrue p, all" + PTEST

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D121180
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/sve-cmp-folds.ll diff | blob | history
Domain: System / Toolchain;