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(parent: acab4b6) | patch
[RISCV] Make custom isel for (add X, imm) used by load/stores more selective.
authorCraig Topper <craig.topper@sifive.com>
Thu, 30 Jun 2022 21:11:09 +0000 (14:11 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 30 Jun 2022 21:20:11 +0000 (14:20 -0700)
commit354e04554a35c1007c7bbf0c7477bdea08642cfc
tree0f48c593a936fae3587d88cf9be679ac8083d811tree | snapshot
parentacab4b69a470eae9d4e5d462378062fda8d1f960commit | diff
[RISCV] Make custom isel for (add X, imm) used by load/stores more selective.

Only handle immediates that would produce an ADDI or ADDIW of Lo12
as the final instruction in their materialization.

As the test change show this removes immediates that materialize
with lui+addiw that is not the same as lui+addi.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/mem64.ll diff | blob | history
Domain: System / Toolchain;