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mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode
authorPratyush Yadav <p.yadav@ti.com>
Mon, 5 Oct 2020 15:31:30 +0000 (21:01 +0530)
committerVignesh Raghavendra <vigneshr@ti.com>
Mon, 9 Nov 2020 06:26:16 +0000 (11:56 +0530)
commit354b412967016e2f99fb2d5113e7b92b539f33b6
tree1cf7a23c5db9609205c1b9b19d30e0c0b8cd173dtree | snapshot
parent6c6a2b2b8ed6dd1ad1a318afd1035777a73936e0commit | diff
mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

Some controllers, like the cadence qspi controller, have trouble reading
only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in
DTR mode, and then discard the second byte.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20201005153138.6437-8-p.yadav@ti.com
drivers/mtd/spi-nor/core.c diff | blob | history
Domain: System / Kernel;