[X86] Add vector support to targetShrinkDemandedConstant for OR/XOR opcodes
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 29 Jun 2020 11:18:27 +0000 (12:18 +0100)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 29 Jun 2020 11:19:05 +0000 (12:19 +0100)
commit3521ecf1f8a3cf5e4811f93a9a809fc722462bbf
tree78baacc782547a33fc710d8d8fd17b708725058a
parent7f3d9cc1c059688b70cb35e673100c9eeadc4c46
[X86] Add vector support to targetShrinkDemandedConstant for OR/XOR opcodes

If a constant is only allsignbits in the demanded/active bits, then sign extend it to an allsignbits bool pattern for OR/XOR ops.

This also requires SimplifyDemandedBits XOR handling to be modified to call ShrinkDemandedConstant on any (non-NOT) XOR pattern to account for non-splat cases.

Next step towards fixing PR45808 - with this patch we now get a <-1,-1,0,0> v4i64 constant instead of <1,1,0,0>.

Differential Revision: https://reviews.llvm.org/D82257
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/promote-cmp.ll
llvm/test/CodeGen/X86/setcc-lowering.ll