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(parent: 509344b) | patch
x86, cacheinfo: Fix dependency of AMD L3 CID
authorAndreas Herrmann <andreas.herrmann3@amd.com>
Fri, 17 Sep 2010 16:07:45 +0000 (18:07 +0200)
committerH. Peter Anvin <hpa@linux.intel.com>
Fri, 17 Sep 2010 20:25:56 +0000 (13:25 -0700)
commit3518dd14ca888085797ca8d3a9e11c8ef9e7ae68
treec5812562f32cacffc1bf2b95f4e5242dea1e1c78tree | snapshot
parent509344b8b4d365b7ff3bce97198d83a57b7c3f31commit | diff
x86, cacheinfo: Fix dependency of AMD L3 CID

L3 cache index disable code uses PCI accesses to AMD northbridge functions.
Currently the code is #ifdef CONFIG_CPU_SUP_AMD.
But it should be #if (defined(CONFIG_CPU_SUP_AMD) && defined(CONFIG_PCI))
which in the end is a dependency to K8_NB.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100917160744.GF4958@loge.amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
arch/x86/kernel/cpu/intel_cacheinfo.c diff | blob | history
Domain: System / Kernel;