projects / platform / kernel / linux-exynos.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9326947) | patch
clk: tegra: Fix ISP clock modelling
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Thu, 23 Feb 2017 10:44:39 +0000 (12:44 +0200)
committerThierry Reding <treding@nvidia.com>
Mon, 20 Mar 2017 13:04:45 +0000 (14:04 +0100)
commit34ac2c278b306cc3006dd5cbfaff4ec52065bf6f
tree1cac5e108c4f0c050fa796ed682777126beab16ctree | snapshot
parent9326947f2215e1816a9133b0b47e4c9200552777commit | diff
clk: tegra: Fix ISP clock modelling

The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model
this as 1 mux/divider clock and child gate clocks.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-id.h diff | blob | history
drivers/clk/tegra/clk-tegra-periph.c diff | blob | history
drivers/clk/tegra/clk-tegra210.c diff | blob | history
include/dt-bindings/clock/tegra210-car.h diff | blob | history
Domain: System / Kernel;