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dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Tue, 14 Mar 2023 12:44:00 +0000 (20:44 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Tue, 28 Mar 2023 03:23:06 +0000 (12:23 +0900)
commit349110b14a17ed18c4f65ad9ff8f0183a7f699b7
tree8d0079f5957e5d5503e2ca4955d237a3a62d0d38tree | snapshot
parentae808ff603a408fe77cb6e5c169401002940915ccommit | diff
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator

Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | history
include/dt-bindings/reset/starfive,jh7110-crg.h diff | blob | history
Domain: System / Kernel;