drm/msm/dpu: Fix address of SM8150 PINGPONG5 IRQ register
authorRobert Foss <robert.foss@linaro.org>
Thu, 19 Aug 2021 13:36:36 +0000 (15:36 +0200)
committerRob Clark <robdclark@chromium.org>
Tue, 12 Oct 2021 00:30:53 +0000 (17:30 -0700)
commit3431c17b75c62f8a28db887441bced2007bd3ffc
treef49313c559b635208cd40f9818c866c04dd89fea
parent6a7e0b0e9fb839caa7c7f25bcf91a95b1c2cbef1
drm/msm/dpu: Fix address of SM8150 PINGPONG5 IRQ register

Both PINGPONG4 and PINGPONG5 IRQ registers are using the
same address, which is incorrect. PINGPONG4 should use the
register offset 30, and PINGPONG5 should use the register
offset 31 according to the downstream driver.

Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw catalog")
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210819133636.2045766-1-robert.foss@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c