clk: qcom: ipq8074: SW workaround for UBI32 PLL lock
authorRobert Marko <robimarko@gmail.com>
Sun, 15 May 2022 21:00:39 +0000 (23:00 +0200)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Thu, 30 Jun 2022 23:06:13 +0000 (18:06 -0500)
commit3401ea2856ef84f39b75f0dc5ebcaeda81cb90ec
treedec2ab59627dd79a3dae3048f96a56855443888a
parentca41ec1b30434636c56c5600b24a8d964d359d9c
clk: qcom: ipq8074: SW workaround for UBI32 PLL lock

UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it
will cause the wait_for_pll() to timeout and thus return the error
indicating that the PLL failed to lock.

This is bug in Huayra PLL HW for which SW workaround
is to set bit 26 of TEST_CTL register.

This is ported from the QCA 5.4 based downstream kernel.

Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-2-robimarko@gmail.com
drivers/clk/qcom/gcc-ipq8074.c