85xx: Fix enabling of L1 cache parity on secondary cores
authorKumar Gala <galak@kernel.crashing.org>
Fri, 26 Mar 2010 20:14:43 +0000 (15:14 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 30 Mar 2010 15:48:30 +0000 (10:48 -0500)
commit33f57bd553edf29dffef5a6c7d76e169c79a6049
treecae931b06803cf6ff873209a52e5e7dd706beb26
parent060f28532b09dd3d2c78423bdd809ac768a27629
85xx: Fix enabling of L1 cache parity on secondary cores

Use the same code between primary and secondary cores to init the
L1 cache.  We were not enabling cache parity on the secondary cores.

Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks.  Than enables the cache and
makes sure its enabled before continuing.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
cpu/mpc85xx/release.S
cpu/mpc85xx/start.S
include/asm-ppc/processor.h