TEST mfld pmu: add arch/x86/platform/mfld/pmu.h

TEST mfld pmu: add arch/x86/platform/mfld/pmu.h

from UMG 2.6.35 tree: arch/x86/kernel/mid_pmu.h

commit 1df781ef9bbc9b0fc453537da2a3b1861f363138
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Thu Jun 23 04:58:43 2011 +0530

    mid_pmu:  sparse warnings fixed

    BZ: 3856

    Fixed the following sparse warnings.

    arch/x86/kernel/mid_pmu.c:302:18: warning: symbol 'pmu_wake_lock' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1126:15: warning: symbol 'pmu_get_cstate' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1813:3: warning: symbol 'medfield_lsses' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1874:5: warning: symbol 'medfield_lsses_num' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1876:6: warning: symbol 'lss_device_status' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:2368:5: warning: symbol 'mid_suspend' was not declared. Should it be static?

    fixed make namespacecheck issues.

    Change-Id: I7731a0391b1433a7ecfa28bdd3265591d1389495
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 5e73c57d106f8c766a5a06221e2817a7c9a5b393
Author: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
Date:   Thu Jun 16 16:59:39 2011 -0700

    Revert "Revert "mid_pmu: Moving NC power management logic to OSPM""

    BZ: 1957

    Currently the PM for north complex was done independently by Gfx and ISP drivers.
    There was no synchronization between ISP and Gfx while sending the PM cmd.

    OSPM patch to provide an API, pmu_nc_set_power_state. This API will take care
    of talking to P-unit and getting the corresponding power islands to ON/OFF.
    Gfx and ISP drivers need to use this API in their drivers.

    Change-Id: I628dd8b03f5d09607e3c931e29943fcdb73613cb
    Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
    Signed-off-by: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
commit dd6db50f98b6c0d368b9315124b65ec3b1aae2a1
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date:   Thu Jun 23 18:29:21 2011 +0200

    Revert "Revert "mid_pmu: pick correct D0ix states in choose_state""

    BZ: 2102
    This reverts commit 41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c.

    Change-Id: I5aa5658cf28696a3c79a939ea8644a3b3c4d73f0

commit 41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c
Author: Marie-Celine Dubut <marie.celinex.dubut@intel.com>
Date:   Wed Jun 22 12:44:06 2011 +0200

    Revert "mid_pmu: pick correct D0ix states in choose_state"

    BZ 2102
    This reverts commit c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d.

    Change-Id: I7e7aed5071adabc824c303628ba855031892e70a

commit c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Jun 1 13:19:54 2011 +0530

    mid_pmu: pick correct D0ix states in choose_state

    BZ: 2102

    currently pmu_pci_choose_state return PCI_D3hot for all devices.
    For some of devices, it may not be possible to support PCI_D3hot state.
    eg., HSU needs to be put in D0i1, chaabi needs to be put in
    D0i2. It is not appropriate to always choose D0i3 for all devices

    We choose the correct state that is appropriate for each device
    for the  platform.

    This patch should be used only with a FW that is capable of supporting
    Chaabi D0i2.

    Change-Id: Ief7b64bc1ec37d4452ce3222454bdd6102d54c10
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit c4e73f14acb7ffd39a5d965fc23b1f01673363b8
Author: Hari Kanigeri <hari.k.kanigeri@intel.com>
Date:   Fri Jun 3 11:27:13 2011 -0600

    mid_pmu: fix checkpatch violations and some cleanup in exit paths

    BZ: 3066

    Fix the following:

    1. Checkpatch violations and cosmetic changes.
    2. fix correct cleanup in the exit paths of the function mid_pmu_probe

    Below log is related to checkpatch violations.

    1. Checkpatch violations
    =========================

    ERROR: space required before the open parenthesis '('
    +	if(pdev->device == 0x81c || pdev->device == 0x81b)

    WARNING: line over 80 characters
    +	for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}

    ERROR: trailing statements should be on next line
    +	for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}

    WARNING: braces {} are not necessary for single statement blocks
    +	for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}

    WARNING: line over 80 characters
    +static pci_power_t  pmu_pci_get_weakest_state_for_lss(int lss_index, struct pci_dev *pdev, pci_power_t state)

    <cut here for brewity, please run checkpatch to see a complete list>

    total: 122 errors, 14 warnings, 2340 lines checked

    Change-Id: I1cdbd6a8b70d303611f0cd426ce63235010d0a07
    Signed-off-by: Hari Kanigeri <hari.k.kanigeri@intel.com>
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit d332d4a59c01e1774cd4fdc28d97fe4d865989ee
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Thu Feb 16 22:36:00 2006 +0530

    pmu: adding atomisp as part of entry criterion for S0i3

    BZ: 1339

    In current build we dont look at the isp runtime status before
    we enter S0i3 state. In this patch we check for the camera status
    in addition to all other device states that we check today in S0i3.

    Change-Id: If3f024fa22d0d744160b961e637e2b1c25e5e1c9
    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit 53f93b022da79eadc22a2ac5c3adade98380cf84
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon May 16 00:26:13 2011 +0530

    mid_pmu: demote c6 to c4 while s0ix is in progress

    BZ: 2120

    While S0ix aborts SCU waits for Ack_C6 timeout, IA comes out of
    mwait and since the SCU is still waiting for Ack_C6 the S0ix
    ACK_C6 timeout error interrupt is not recieved, meanwhile a new
    C6 could be triggered from IA and this could trigger a Ack_C6
    SCU can mistake this Ack_C6 as a ack for the previously aborted
    S0ix and continue S0ix flow. This is not correct.

    We check if the system is in S0ix progress state by checking
    scu_ready_sem if its already acquired that means S0ix is in
    progress and the subsequent C6 should be demoted to C4's

    Change-Id: I1b60824b28f9b6579dd551faa8fe485d2074b712
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 654da78fa8f45bcf4d64d9c0ea115d589f4374c4
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Sun May 15 23:44:23 2011 +0530

    mid_pmu: c6 offload msr bit cleanup

    BZ: 2116

    We were using magic number for wmsr(0x120) for setting/clearing
    offload bit.

    Fixed this by creating #defines

    Change-Id: I5fe4ec0568e48d12fe30074f8eebbc2a6411b4d8
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 8118849a0329d0e73761562443ae25c8b1cd3bf9
Author: Fengwei Yin <fengwei.yin@intel.com>
Date:   Sun May 22 11:57:12 2011 +0800

    Revert "mid_pmu:  Moving NC power management logic to OSPM"

    BZ: 2470

    This reverts commit 594c7f0327dd02985fbcde1e0bd83c98e684097f.

commit 594c7f0327dd02985fbcde1e0bd83c98e684097f
Author: Sujith Thomas <sthoma3@umg-lab1.iind.intel.com>
Date:   Thu May 12 10:51:38 2011 +0530

    mid_pmu:  Moving NC power management logic to OSPM

    BZ: 1957

    Currently the PM for north complex was done independently by Gfx and ISP drivers.
    There was no synchronization between ISP and Gfx while sending the PM cmd.

    OSPM patch to provide an API, pmu_nc_set_power_state.
    This API will take care of talking to P-unit and getting the corresponding power
    islands to ON/OFF. Gfx and ISP drivers need to use this API in their drivers.

    Change-Id: I302c9a7a6bb10ae572d340affb2502443d6178fc
    Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
commit cba613f2bde66236706b9c0ba7f1fe6b5ff14ad7
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Tue May 10 16:22:10 2011 +0530

    pmu:  renaming lss after new wkc implementation in scu

    BZ 1756

    This patch we are re assigning some of the lss to new lss
    based on the WKC implementation in scu.

    Change-Id: Ic7a9adf37194182b424dcdcc0d61cb09bba4a7a5
    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit 821d3f9513a5126201531e804c98b3618456d637
Author: Jean-Pierre Stierlin <jean-pierrex.stierlin@intel.com>
Date:   Thu May 5 18:19:43 2011 +0200

    OSPM: Add HSI as wake source in s0i3

    BZ: 1705

    HSI wake event was disabled in SCU configuration

    Revert a hack to disable HSI wake event to the SCU due to spurious interrupts.

    Change-Id: I2e9173fdf79fa158394a4b0b5894f643d3a43b8f

commit cfda66e44bc142f836c2e550211997759aa0d8e2
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Mar 30 16:23:28 2011 +0530

    mid_pmu: cleanup added explicit LSS ids for s0ix entry

    Currently the LSS that need to be checked for S0ix/LPMP3
    entry is hardcoded making it difficult to read the sub
    system values.

    Added #defines for all the sub system LSS id's, using this
    defined the target config values to check against the SSS
    register values, that tells which subsystems need to in D0i3
    to issue S0i1/3 or LPMP3 commands.

    Also added a way to keep always ON LSS to be in D0i0.

    Added check for Keyboard, UART0/1/2 LSS in S0i1/lpmp3/S0i3 SSS
    config registers.

    Removed LSS 40, 41 from ignore_lss list.

    Change-Id: Ifd28b58f11c66232dc2993b3946c672bbe9931a3
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 885ebc4f559cdaa19b3dddd02faa2dba246ae689
Author: Sundar Iyer <sundar.iyer@intel.com>
Date:   Tue Mar 22 15:03:51 2011 +0530

    mid_pmu: correct D0ix states during S0i3

    Enable the UART0/1/2 and the KBD modules to be put into D0i3 states
    during the S0i3.

    Change-Id: Idec4907699ba23506900a249a130cecaed85dc82
    Signed-off-by: Sundar Iyer <sundar.iyer@intel.com>
commit 56ab6e9474f2e04f50ddede8f2b6db9e1dc852c1
Author: Sundar Iyer <sundar.iyer@intel.com>
Date:   Wed Mar 9 13:19:29 2011 +0530

    mid_pmu: correct USB Dx state during S0i3 entry

    Enable D0i3 state for the USB during S0i3 entry. Making this
    change realizes power figures for the USB rail from ~16mW to ~.4mW

    Signed-off-by: Sundar Iyer <sundar.iyer@intel.com>
commit 0c2cb76662387a575c6f41b9f91a85cd76064f55
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Sat Feb 5 14:52:41 2011 +0100

    mid_pmu: cleanup: fix sparse check warnings

    moved all #defines to mid_pmu.h

    fixed warnings after installing sparse tool

    Fixed the following warnings from sparse.
    with make C=2 >& sparse.log command.

    arch/x86/kernel/mid_pmu.c:46:3: warning: symbol 'pci_dev_index' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1175:70: warning: incorrect type in argument 2 (different address spaces)
    arch/x86/kernel/mid_pmu.c:1175:70:    expected void volatile [noderef] <asn:2>*addr
    arch/x86/kernel/mid_pmu.c:1175:70:    got unsigned int *
    arch/x86/kernel/mid_pmu.c:1180:76: warning: incorrect type in argument 2 (different address spaces)
    arch/x86/kernel/mid_pmu.c:1180:76:    expected void volatile [noderef] <asn:2>*addr
    arch/x86/kernel/mid_pmu.c:1180:76:    got unsigned int *
    arch/x86/kernel/mid_pmu.c:322:5: warning: symbol 'get_target_platform_state' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:691:6: warning: symbol 'mfld_s0i1_enter' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:717:5: warning: symbol 'mfld_s0i3_enter' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:844:5: warning: symbol 'is_msi_enabled' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1191:59:    got unsigned int *
    arch/x86/kernel/mid_pmu.c:1502:13: warning: incorrect type in assignment (different address spaces)
    arch/x86/kernel/mid_pmu.c:1502:13:    expected struct mrst_pmu_reg *pmu
    arch/x86/kernel/mid_pmu.c:1502:13:    got void [noderef] <asn:2>*
    arch/x86/kernel/mid_pmu.c:1567:27:    expected void [noderef] <asn:2>*<noident>
    arch/x86/kernel/mid_pmu.c:1567:27:    got struct mrst_pmu_reg *static [toplevel] *<noident>
    ...
    and similar warnings.

    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 33d19d30ff22685f18f184183b1e675d8fe94fea
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon Jan 17 08:22:32 2011 +0100

    mid_pmu: driver that controls pmus of intel_mid platforms

    Mobile Internet Devices based on the Intel "Medfield" platform have two
    Platform Management Units (PMU). The first PMU (pmu1) comprises of the
    Silverthorne CPU, Graphics, Video encode/decode and Display engines,
    The second PMU (pmu2) is the IO hub.

    The Platform Management Unit (PMU) driver is a Medfield-specific power
    management driver. Intel's  MID provides fine tuned knobs for
    platform level. Intel's Medfield MID provides control for platform
    level power management and the OS Power Management solution guides the
    power states that the subsystems and CPU needs to be in depending on the
    current usage and power policy set by the user.

    The purpose of the Medfield Power Management architecture is to turn
    off subsystems without affecting the end user functionality/usability of
    the system.

    The Power Management scheme uses the concept of operating modes, which
    define the configuration of all the subsystems under each of the usage model
    that the user might put the system in. Based on current platform usage,
    OSPM decides the target power states for the sub systems, and the PMU
    driver implements the OS-HW interface.

    "Intel" Medfield PMU driver interfaces with two power management units
    (PMU) pmu1 & pmu2. On receiving commands PMU driver interfaces
    with the pmu1 & pmu2 via a well defined register interface to drive the
    required power  management flows.

    This patch contains:
    - key definitions for the PMU driver.
    - core logic of the PMU driver as it interfaces with pmu1 & pmu2 for
    different platform power management flows.

    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
    Signed-off-by: Rajeev D Muralidhar <rajeev.d.muralidhar@intel.com>
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>