drm/i915: Implement workaround for CDCLK PLL disable/enable
authorStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Mon, 30 Jan 2023 13:58:36 +0000 (15:58 +0200)
committerStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Tue, 31 Jan 2023 08:55:02 +0000 (10:55 +0200)
commit33d0c67dcbb045cbbbba9d41fa6e4b1f73bf3888
tree1f15a13a60205a1d19986cc12799e9d9d76e71f4
parent9c608cf39b96666ecbc163e3f6197f6d8ea78e56
drm/i915: Implement workaround for CDCLK PLL disable/enable

It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.

v2: - Added WA number comment(Rodrigo Vivi)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130135836.12738-1-stanislav.lisovskiy@intel.com
drivers/gpu/drm/i915/display/intel_cdclk.c