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[RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]
authorLuke Lau <luke@igalia.com>
Mon, 17 Jul 2023 11:11:21 +0000 (12:11 +0100)
committerLuke Lau <luke@igalia.com>
Fri, 21 Jul 2023 09:22:46 +0000 (10:22 +0100)
commit33a83c5486d599e00f4c6ba35b12c1e74bc0554b
treee77313170bc3ff9847c741cc6d2cec17c59a41d3tree | snapshot
parent5c9db625873d9cbf891115f37265d093845b7cc7commit | diff
[RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

These correspond to ROTL/ROTR nodes

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155439
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h diff | blob | history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll [new file with mode: 0644] blob
Domain: System / Toolchain;