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(parent: 8606f96) | patch
clk: sunxi: Add Allwinner H6 CLK driver
authorJagan Teki <jagan@amarulasolutions.com>
Mon, 31 Dec 2018 10:05:01 +0000 (15:35 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Fri, 18 Jan 2019 16:49:09 +0000 (22:19 +0530)
commit337fcdc06bad484d3af08e0fd0876e22a09358ce
treedf491f67132d0a4ac89e6e71bebf9237098b0440tree | snapshot
parent8606f960d4e40f1fbd7fb7e1be30c924dbb9dba0commit | diff
clk: sunxi: Add Allwinner H6 CLK driver

Add initial clock driver for Allwinner H6.

- Implement UART bus clocks via ccu_clk_gate table for
  H6, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
drivers/clk/sunxi/Kconfig diff | blob | history
drivers/clk/sunxi/Makefile diff | blob | history
drivers/clk/sunxi/clk_h6.c [new file with mode: 0644] blob
Domain: System / Kernel;