RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2
authorAndrew Waterman <andrew@sifive.com>
Sun, 24 Sep 2017 01:04:16 +0000 (18:04 -0700)
committerPalmer Dabbelt <palmer@dabbelt.com>
Tue, 24 Oct 2017 15:02:46 +0000 (08:02 -0700)
commit3342be5dabeeaf2218dfbf4d38f92214612436f4
treee39053086e5e3873823abd2d77e630fc32926fe7
parent3779bbe01b4ec1e5ae0a5c555f838999ba88ac50
RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2

This matches the ISA specification.  This also adds two tests: one to
make sure the assembler rejects invalid 'c.lui's, and one to make sure
we only relax valid 'c.lui's.

bfd/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
        when rd is x0.

include/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
        immediate 0.

gas/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * testsuite/gas/riscv/c-lui-fail.d: New testcase.
        gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
        gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
        gas/testsuite/gas/riscv/riscv.exp: Likewise.

ld/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
        ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
        ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
13 files changed:
bfd/ChangeLog
bfd/elfnn-riscv.c
gas/ChangeLog
gas/testsuite/gas/riscv/c-lui-fail.d [new file with mode: 0644]
gas/testsuite/gas/riscv/c-lui-fail.l [new file with mode: 0644]
gas/testsuite/gas/riscv/c-lui-fail.s [new file with mode: 0644]
gas/testsuite/gas/riscv/riscv.exp
include/ChangeLog
include/opcode/riscv.h
ld/ChangeLog
ld/testsuite/ld-riscv-elf/c-lui.d [new file with mode: 0644]
ld/testsuite/ld-riscv-elf/c-lui.s [new file with mode: 0644]
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp [new file with mode: 0644]