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(parent: 2fda36a) | patch
[X86] Remove PALIGNR/VALIGN handling from combineBitcastForMaskedOp and move to isel...
authorCraig Topper <craig.topper@intel.com>
Fri, 3 Nov 2017 06:48:02 +0000 (06:48 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 3 Nov 2017 06:48:02 +0000 (06:48 +0000)
commit333897ec31d752a4cf4d27c71b9a37d1cfd7dfad
tree3336e5fda23872eefeaaa02be63025f7977b6f62tree | snapshot
parent2fda36a18e2fa97067bb976a7727e5b25afc953fcommit | diff
[X86] Remove PALIGNR/VALIGN handling from combineBitcastForMaskedOp and move to isel patterns instead. Prefer 128-bit VALIGND/VALIGNQ over PALIGNR during lowering when possible.

llvm-svn: 317299
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/lib/Target/X86/X86InstrAVX512.td diff | blob | history
llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll diff | blob | history
Domain: System / Toolchain;