clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'
authorShawn Guo <shawn.guo@linaro.org>
Wed, 27 Sep 2017 18:59:40 +0000 (11:59 -0700)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 14 Nov 2017 17:49:00 +0000 (09:49 -0800)
commit3320f39bee899b68d4f35220764b2ab213374708
treea42559154686c07f81da8e73a1af26d6781feacd
parent90c42090c0da3a77057ba777e2d3f8d16e55aabc
clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'

Other than 'mmc_mux', 'clk_sdio0_ciu' uses a different parent mux clock.
Let's add this mux clock as 'sdio0_mux', and correct the parent of
'clk_sdio0_ciu' to be it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/hisilicon/crg-hi3798cv200.c