clk: renesas: rzg2l: Add support to handle coupled clocks
authorBiju Das <biju.das.jz@bp.renesas.com>
Wed, 22 Sep 2021 15:51:44 +0000 (16:51 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 24 Sep 2021 13:11:05 +0000 (15:11 +0200)
commit32897e6fff196a5de4981030466ae391dfe56c7b
treeeb20f75de0e391ec47e7d16143910ea6f56e1ff5
parent70a4af3662e073768a68a7ed5a82f49677cbde0c
clk: renesas: rzg2l: Add support to handle coupled clocks

The AXI and CHI clocks use the same register bit for controlling clock
output. Add a new clock type for coupled clocks, which sets the
CPG_CLKON_ETH.CLK[01]_ON bit when at least one clock is enabled, and
clears the bit only when both clocks are disabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/rzg2l-cpg.c
drivers/clk/renesas/rzg2l-cpg.h