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(parent: 6640594) | patch
upstream: [media] mt9p031: Add support for PLL bypass
authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Sun, 9 Feb 2014 20:31:47 +0000 (17:31 -0300)
committerChanho Park <chanho61.park@samsung.com>
Thu, 7 Aug 2014 05:26:34 +0000 (14:26 +0900)
commit326e1a5f542be2275ab130838fb8c4e54323c71f
treee5d1ced260703b3f4e793bb8e2195b9378f8510dtree | snapshot
parent6640594cd1e8c2804eb9f9c5fd462557cec05e7dcommit | diff
upstream: [media] mt9p031: Add support for PLL bypass

When the input clock frequency is out of bounds for the PLL, bypass the
PLL and just divide the input clock to achieve the requested output
frequency.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
drivers/media/i2c/mt9p031.c diff | blob | history
Domain: System / Kernel;