[RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.
authorCraig Topper <craig.topper@sifive.com>
Mon, 22 Feb 2021 22:36:44 +0000 (14:36 -0800)
committerCraig Topper <craig.topper@sifive.com>
Mon, 22 Feb 2021 22:56:22 +0000 (14:56 -0800)
commit3231607ce95fb34adcddbdd55f8bb00b4a2a2125
treec56027da126350440009e542cf2968d62c3e0a16
parentfe2dcd89acfd9301a230e38e9030734553baa8dc
[RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.

An i64 AssertZExt from a type smaller than i32 has at least 33
leading zeros which mean it has at least 33 sign bits.

Since we have a couple patterns that use two sexti32, I've
switched to a ComplexPattern so tablegen didn't have to generate
9 different permutations.

As noted in the FIXME, maybe we should just call computeNumSignBits,
but we don't have tests that benefit from that yet.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D97130
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoM.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll