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author	Amara Emerson <amara@apple.com>
	Sat, 3 Oct 2020 01:30:53 +0000 (18:30 -0700)
committer	Amara Emerson <amara@apple.com>
	Wed, 7 Oct 2020 17:36:44 +0000 (10:36 -0700)
commit	322d0afd875df66b36e4810a2b95c20a8f22ab9b
tree	1b00de8cb447daca52dff1e35eeec1f15f122687	tree \| snapshot
parent	19bc894da12a9229b3e8cfb11a0281786f07ab6c	commit \| diff

[llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics.

This change renames the intrinsics to not have "experimental" in the name.

The autoupgrader will handle legacy intrinsics.

Relevant ML thread: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140729.html

Differential Revision: https://reviews.llvm.org/D88787

182 files changed:

llvm/docs/LangRef.rst		diff \| blob \| history
llvm/docs/ReleaseNotes.rst		diff \| blob \| history
llvm/include/llvm/CodeGen/BasicTTIImpl.h		diff \| blob \| history
llvm/include/llvm/IR/Intrinsics.td		diff \| blob \| history
llvm/lib/Analysis/ConstantFolding.cpp		diff \| blob \| history
llvm/lib/CodeGen/ExpandReductions.cpp		diff \| blob \| history
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp		diff \| blob \| history
llvm/lib/IR/AutoUpgrade.cpp		diff \| blob \| history
llvm/lib/IR/IRBuilder.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h		diff \| blob \| history
llvm/lib/Target/ARM/ARMTargetTransformInfo.h		diff \| blob \| history
llvm/lib/Target/ARM/MVETailPredication.cpp		diff \| blob \| history
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp		diff \| blob \| history
llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp		diff \| blob \| history
llvm/test/Analysis/CostModel/AArch64/vector-reduce.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/ARM/reduce-add.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/ARM/reduce-smax.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/ARM/reduce-smin.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/ARM/reduce-umax.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/ARM/reduce-umin.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-add.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-and.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-fmax.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-fmin.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-mul.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-or.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-smax.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-smin.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-umax.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-umin.ll		diff \| blob \| history
llvm/test/Analysis/CostModel/X86/reduce-xor.ll		diff \| blob \| history
llvm/test/Assembler/invalid-vecreduce.ll		diff \| blob \| history
llvm/test/Bitcode/upgrade-vecreduce-intrinsics.ll		diff \| blob \| history
llvm/test/Bitcode/upgrade-vecreduce-intrinsics.ll.bc		diff \| blob \| history
llvm/test/CodeGen/AArch64/aarch64-addv.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/arm64-vabs.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/neon-dot-product.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-bool.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-fadd.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll		diff \| blob \| history
llvm/test/CodeGen/Generic/expand-experimental-reductions.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-reduce.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-reduce-mve-tail.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vaddv.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-bit.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vecreduce-mul.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vmaxv.ll		diff \| blob \| history
llvm/test/CodeGen/X86/haddsub.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pr45378.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-add.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-and-bool.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-and-cmp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-and.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fadd.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmax-fmin-fast.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-fmul.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-mul.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-or-bool.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-or.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-smax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-smin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-umax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-umin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-xor.ll		diff \| blob \| history
llvm/test/Instrumentation/MemorySanitizer/reduce.ll	[moved from llvm/test/Instrumentation/MemorySanitizer/experimental-reduce.ll with 66% similarity]	diff \| blob \| history
llvm/test/Transforms/InstCombine/vector-reductions.ll		diff \| blob \| history
llvm/test/Transforms/InstSimplify/ConstProp/vecreduce.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/AArch64/reduction-small-size.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/X86/pr35432.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/X86/pr42674.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/reduction-inloop.ll		diff \| blob \| history
llvm/test/Transforms/LoopVectorize/reduction-predselect.ll		diff \| blob \| history
llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/reassociated-loads.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/reduction.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/reduction_loads.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll		diff \| blob \| history
llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll		diff \| blob \| history
mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td		diff \| blob \| history
mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td		diff \| blob \| history
mlir/include/mlir/Dialect/Vector/VectorOps.td		diff \| blob \| history
mlir/integration_test/Dialect/LLVMIR/CPU/test-vector-reductions-fp.mlir		diff \| blob \| history
mlir/integration_test/Dialect/LLVMIR/CPU/test-vector-reductions-int.mlir		diff \| blob \| history
mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp		diff \| blob \| history
mlir/test/Conversion/VectorToLLVM/vector-reduction-to-llvm.mlir		diff \| blob \| history
mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir		diff \| blob \| history
mlir/test/Target/llvmir-intrinsics.mlir		diff \| blob \| history

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