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(parent: 11f1a55) | patch
drm/amd/display: Add otg vertical interrupt0 support in DCN1.0
authorWayne Lin <Wayne.Lin@amd.com>
Wed, 20 Jan 2021 09:22:30 +0000 (17:22 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 9 Feb 2021 20:29:02 +0000 (15:29 -0500)
commit320eca62fe61ca1efded0d2a95392e4f20e53b46
tree14516c2e828bb9b15483846bafd8f4bfc8a9352ctree | snapshot
parent11f1a5538ba5f1c4462c806560a343b5258f22b8commit | diff
drm/amd/display: Add otg vertical interrupt0 support in DCN1.0

[Why & How]
On DCN1.0, need otg vertical line interrupt to get appropriate timing
to achieve specific feature request.

Add otg vertical interrupt0 support for registers which operation is
vertical sensitive.

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c diff | blob | history
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c diff | blob | history
drivers/gpu/drm/amd/display/dc/irq_types.h diff | blob | history
Domain: System / Kernel;