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[RISCV] Remove redundant test cases for index segment load (2/8).
authorHsiangkai Wang <kai.wang@sifive.com>
Fri, 19 Feb 2021 03:07:36 +0000 (11:07 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Fri, 19 Feb 2021 03:56:08 +0000 (11:56 +0800)
commit320250e4865756545b4187a74faac656120c678b
tree810950f33ee2ed770310d5820a92514675867d70tree | snapshot
parenta32c79ce2c355decbf6fd06b492044828c1c957dcommit | diff
[RISCV] Remove redundant test cases for index segment load (2/8).
llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll diff | blob | history
Domain: System / Toolchain;