[binutils][aarch64] New SVE_Zm4_11_INDEX operand.
authorMatthew Malcomson <matthew.malcomson@arm.com>
Thu, 9 May 2019 09:29:24 +0000 (10:29 +0100)
committerMatthew Malcomson <matthew.malcomson@arm.com>
Thu, 9 May 2019 09:29:24 +0000 (10:29 +0100)
commit31e36ab341498bb477a46a0475100ec5d471c4f2
treefb56a49e0b0fd35ecabbf84b3dc7f128ba84441d
parent1be5f94f9c85821287b9ae423f738a8bab499526
[binutils][aarch64] New SVE_Zm4_11_INDEX operand.

This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
gas/ChangeLog
gas/config/tc-aarch64.c
include/ChangeLog
include/opcode/aarch64.h
opcodes/ChangeLog
opcodes/aarch64-asm-2.c
opcodes/aarch64-dis-2.c
opcodes/aarch64-opc-2.c
opcodes/aarch64-opc.c
opcodes/aarch64-opc.h
opcodes/aarch64-tbl.h