review.tizen.org Git - platform/upstream/llvm.git/commit

Revert "[RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block"

This reverts commit 0ba41dd3806e658e67acb63353fd5540f2bf333c.

14 files changed:

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-transpose.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll		diff \| blob \| history

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