powerpc: mpc85xx: Fix static TLB table for SDRAM
authorYork Sun <york.sun@nxp.com>
Tue, 5 Dec 2017 18:57:54 +0000 (10:57 -0800)
committerYork Sun <york.sun@nxp.com>
Wed, 6 Dec 2017 22:54:12 +0000 (14:54 -0800)
commit316f0d0f8f3cbeeefda043e69f3e4e6aa57f7f1d
treee4201de6e106653a02a04c13f21cf3685bc878ee
parent0f2296bab1417faa5973e6d6690c8be0f83ecd08
powerpc: mpc85xx: Fix static TLB table for SDRAM

Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.

Signed-off-by: York Sun <york.sun@nxp.com>
22 files changed:
board/Arcturus/ucp1020/tlb.c
board/freescale/b4860qds/tlb.c
board/freescale/bsc9131rdb/tlb.c
board/freescale/bsc9132qds/tlb.c
board/freescale/c29xpcie/tlb.c
board/freescale/mpc8541cds/tlb.c
board/freescale/mpc8548cds/tlb.c
board/freescale/mpc8568mds/tlb.c
board/freescale/p1010rdb/tlb.c
board/freescale/p1022ds/tlb.c
board/freescale/p1023rdb/tlb.c
board/freescale/p1_p2_rdb_pc/tlb.c
board/freescale/p1_twr/tlb.c
board/freescale/t102xqds/tlb.c
board/freescale/t102xrdb/tlb.c
board/freescale/t104xrdb/tlb.c
board/freescale/t208xqds/tlb.c
board/freescale/t208xrdb/tlb.c
board/freescale/t4qds/tlb.c
board/freescale/t4rdb/tlb.c
board/gdsys/p1022/tlb.c
board/sbc8548/tlb.c