[X86] Add more ISD nodes to handle masked versions of VCVT(T)PD2DQZ128/VCVT(T)PD2UDQZ...
authorCraig Topper <craig.topper@intel.com>
Sun, 13 Jan 2019 02:59:59 +0000 (02:59 +0000)
committerCraig Topper <craig.topper@intel.com>
Sun, 13 Jan 2019 02:59:59 +0000 (02:59 +0000)
commit31156bbdb9b3d27cf762eeec6a1b06db6d6c652c
treeb295c571695f6b2061f310c57a8aa028a86ec20e
parent4561edbec0355b68156fb809551f4dce90fdccb7
[X86] Add more ISD nodes to handle masked versions of VCVT(T)PD2DQZ128/VCVT(T)PD2UDQZ128 which only produce 2 result elements and zeroes the upper elements.

We can't represent this properly with vselect like we normally do. We also have to update the instruction definition to use a VK2WM mask instead of VK4WM to represent this.

Fixes another case from PR34877

llvm-svn: 351018
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/lib/Target/X86/X86IntrinsicsInfo.h