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(parent: c0bb15f) | patch
clk:starfive:Add PLL0 frequency controller
authorxingyu.wu <xingyu.wu@starfivetech.com>
Mon, 11 Jul 2022 08:46:18 +0000 (16:46 +0800)
committerxingyu.wu <xingyu.wu@starfivetech.com>
Wed, 20 Jul 2022 08:47:43 +0000 (16:47 +0800)
commit30eb809e182f1fcfa797f60f9e622ac037486b19
tree77c224f69ffeb96f2a47f19db999e9c20f2f370dtree | snapshot
parentc0bb15fdbe1f0853a202d083c1cc399f8330b97dcommit | diff
clk:starfive:Add PLL0 frequency controller

If enable CONFIG_CLK_STARFIVE_JH7110_PLL, could read or set PLL0 clock's
rate by reading or setting syscon registers.

Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi diff | blob | history
drivers/clk/starfive/Kconfig diff | blob | history
drivers/clk/starfive/Makefile diff | blob | history
drivers/clk/starfive/clk-starfive-jh7110-gen.c diff | blob | history
drivers/clk/starfive/clk-starfive-jh7110-pll.c [new file with mode: 0755] blob
drivers/clk/starfive/clk-starfive-jh7110-pll.h [new file with mode: 0755] blob
drivers/clk/starfive/clk-starfive-jh7110-sys.c diff | blob | history
drivers/clk/starfive/clk-starfive-jh7110.h diff | blob | history
Domain: System / Kernel;