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(parent: 4f2be40) | patch
lib: sbi_hart: Enable hcontext and scontext
authorNylon Chen <nylon.chen@sifive.com>
Fri, 10 Feb 2023 08:52:38 +0000 (16:52 +0800)
committerAnup Patel <anup@brainfault.org>
Mon, 27 Feb 2023 05:52:11 +0000 (11:22 +0530)
commit30ea8069f4c704e67017215f90f74b8588ee9bdf
tree389237de2dabdc8e54ab040c039b76846fa6fbb1tree | snapshot
parent4f2be401025d7f5095dd2a4d2acad0fa60ef15e0commit | diff
lib: sbi_hart: Enable hcontext and scontext

According to the description in "riscv-state-enable[0]", to access
h/scontext in S-Mode, we need to enable the 57th bit.

If it is not enabled, an "illegal instruction" error will occur.

Link: https://github.com/riscv/riscv-state-enable/blob/a28bfae443f350d5b4c42874f428367d5b322ffe/content.adoc
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
include/sbi/riscv_encoding.h diff | blob | history
lib/sbi/sbi_hart.c diff | blob | history
Domain: System / Kernel;