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riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 16 Mar 2023 03:05:14 +0000 (11:05 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Tue, 28 Mar 2023 03:23:09 +0000 (12:23 +0900)
commit304d484defdabef46902bcb99b355791b85f51e9
tree3c2953f996569b16bf3244dc8c45124ee3708e23tree | snapshot
parent85eef7cde825960c6101508ada3db2fff6e85c05commit | diff
riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node

Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi diff | blob | history
Domain: System / Kernel;