[RISCV] Implement pseudo instructions for load/store from a symbol address.
authorKito Cheng <kito.cheng@gmail.com>
Wed, 20 Feb 2019 03:31:32 +0000 (03:31 +0000)
committerKito Cheng <kito.cheng@gmail.com>
Wed, 20 Feb 2019 03:31:32 +0000 (03:31 +0000)
commit303217e8b43d4d299aeb629ecb5b1e060fc77969
tree62dd596999b2506a13fd4b990fb172f102f76d67
parent476e1b9937552b2dde191d0c3a6d3396ef9fa7e7
[RISCV] Implement pseudo instructions for load/store from a symbol address.

Summary:
Those pseudo-instructions are making load/store instructions able to
load/store from/to a symbol, and its always using PC-relative addressing
to generating a symbol address.

Reviewers: asb, apazos, rogfer01, jrtc27

Differential Revision: https://reviews.llvm.org/D50496

llvm-svn: 354430
13 files changed:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/test/MC/RISCV/rv32d-invalid.s
llvm/test/MC/RISCV/rv32f-invalid.s
llvm/test/MC/RISCV/rv32i-invalid.s
llvm/test/MC/RISCV/rv64i-pseudos.s [new file with mode: 0644]
llvm/test/MC/RISCV/rvd-pseudos.s [new file with mode: 0644]
llvm/test/MC/RISCV/rvf-pseudos.s [new file with mode: 0644]
llvm/test/MC/RISCV/rvi-pseudos-invalid.s
llvm/test/MC/RISCV/rvi-pseudos.s