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(parent: 94dcc83) | patch
i915: only use tiled blits on 965+
authorJesse Barnes <jbarnes@hobbes.(none)>
Tue, 1 Jul 2008 23:10:01 +0000 (16:10 -0700)
committerJesse Barnes <jbarnes@virtuousgeek.org>
Tue, 1 Jul 2008 23:10:01 +0000 (16:10 -0700)
commit301d984ea80cb250460d6701c4373cf0af8bf59e
treeb72281b24a13409030190fc6c8e3ac22d8ccada2tree | snapshot
parent94dcc83ad2e8f848a3cac6cdc6f123e676e91cf8commit | diff
i915: only use tiled blits on 965+

When scheduled swaps occur, we need to blit between front & back buffers.  I
the buffers are tiled, we need to set the appropriate XY_SRC_COPY tile bit,
only on 965 chips, since it will cause corruption on pre-965 (e.g. 945).

Bug reported by and fix tested by Tomas Janousek <tomi@nomi.cz>.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
shared-core/i915_irq.c diff | blob | history
Domain: System / Kernel;