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clk: samsung: add new clocks for DMC for Exynos5422 SoC
authorLukasz Luba <l.luba@partner.samsung.com>
Tue, 15 Jan 2019 16:12:16 +0000 (17:12 +0100)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Thu, 6 Jun 2019 13:53:37 +0000 (15:53 +0200)
commit2f57b95caf8f6db7a1295fc9940f91184ced912b
treebd1bcbb0c045b36634ceb8a4af948261f52bcae2tree | snapshot
parent8b4a7acf7b30c811c5cd8b70b615ca8f9efe86cccommit | diff
clk: samsung: add new clocks for DMC for Exynos5422 SoC

This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
GATE entries.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5420.c diff | blob | history
Domain: System / Kernel;