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(parent: cacf3c0) | patch
clk: sunxi: A31: Fix wrong AHB gate number
authorAndre Przywara <andre.przywara@arm.com>
Wed, 23 Jan 2019 00:59:11 +0000 (00:59 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 23 Mar 2019 19:09:47 +0000 (20:09 +0100)
commit2f3b4f96861913008f96ceaedabad7605b164345
treefeecc3925643e697b24afd3779f9639abc0d4f36tree | snapshot
parentcacf3c0d82889b7628e98952bf1207aff398389acommit | diff
clk: sunxi: A31: Fix wrong AHB gate number

[ Upstream commit ee0b27a3a4da0b0ed2318aa092f8856896e9450b ]

According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/sunxi-ng/ccu-sun6i-a31.c diff | blob | history
Domain: System / Kernel;