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(parent: f1ac10c) | patch
iommu/vt-d: Enable 5-level paging mode in the PASID entry
authorSohil Mehta <sohil.mehta@intel.com>
Wed, 20 Dec 2017 19:59:27 +0000 (11:59 -0800)
committerJoerg Roedel <jroedel@suse.de>
Wed, 17 Jan 2018 14:02:50 +0000 (15:02 +0100)
commit2f13eb7c580fcbe3d73ebbe6fb1841381cad0a05
tree9c8c8de8d4b40a3b81e8515f1baef0ac72f1c4bdtree | snapshot
parentf1ac10c24efbbcba0f8dae37ee90d45847f5c5afcommit | diff
iommu/vt-d: Enable 5-level paging mode in the PASID entry

If the CPU has support for 5-level paging enabled and the IOMMU also
supports 5-level paging then enable the 5-level paging mode for first-
level translations - used when SVM is enabled.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/intel-svm.c diff | blob | history
Domain: System / Kernel;