octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon
authorNaveen Mamindlapalli <naveenm@marvell.com>
Sat, 10 Sep 2022 07:54:15 +0000 (13:24 +0530)
committerDavid S. Miller <davem@davemloft.net>
Sat, 17 Sep 2022 19:13:41 +0000 (20:13 +0100)
commit2ef4e45d99b19fb16834616f47d21a9b76b0e5f4
tree66fd6c82bb2345020e7b3cb989f91e5fb53f3dc2
parent2958d17a898416c6193431676f6130b68a2cb9fc
octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon

Errata:
The ptp_clock_hi rollsover to zero one clock cycle before it
reaches one second boundary. As a result, the pps threshold
comparison fails after one second and the pps output signal
won't toggle further.

This patch workarounds the issue by programming the pps_lo_incr
register to 500msec minus one clock cycle period, ensuring that
the pps threshold comparison succeeds at one second rollover
boundary and pps edge toggles. After that point, the driver will
have enough time (~500msec) to reset the pps threshold value.
After each one second boundary, hrtimer is invoked which resets
the pps threshold value.

Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Rakesh Babu Saladi <rsaladi2@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
drivers/net/ethernet/marvell/octeontx2/af/ptp.h
drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c