[X86] Describe wbnoinvd instruction
authorGabor Buella <gabor.buella@intel.com>
Wed, 11 Apr 2018 20:01:57 +0000 (20:01 +0000)
committerGabor Buella <gabor.buella@intel.com>
Wed, 11 Apr 2018 20:01:57 +0000 (20:01 +0000)
commit2ef36f3571c83650f3e1bac42c810c289851d865
treee77e989c86f9fab5b36c9e79361418ad00cb089b
parentd11b6edfc8d870a53995a195c801f5c305e19b1a
[X86] Describe wbnoinvd instruction

Similar to the wbinvd instruction, except this
one does not invalidate caches. Ring 0 only.
The encoding matches a wbinvd instruction with
an F3 prefix.

Reviewers: craig.topper, zvi, ashlykov

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D43816

llvm-svn: 329847
14 files changed:
llvm/include/llvm/IR/IntrinsicsX86.td
llvm/lib/Support/Host.cpp
llvm/lib/Target/X86/X86.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86InstrSystem.td
llvm/lib/Target/X86/X86Subtarget.cpp
llvm/lib/Target/X86/X86Subtarget.h
llvm/test/CodeGen/X86/wbnoinvd-intrinsic.ll [new file with mode: 0644]
llvm/test/MC/Disassembler/X86/x86-16.txt
llvm/test/MC/Disassembler/X86/x86-32.txt
llvm/test/MC/Disassembler/X86/x86-64.txt
llvm/test/MC/X86/x86-16.s
llvm/test/MC/X86/x86-32-coverage.s
llvm/test/MC/X86/x86-64.s