Adding tests and fixing codegen for the Arm 'Aes' and 'ArmBase' hwintrinsics (dotnet...
authorTanner Gooding <tagoo@outlook.com>
Wed, 16 Oct 2019 01:46:44 +0000 (18:46 -0700)
committerGitHub <noreply@github.com>
Wed, 16 Oct 2019 01:46:44 +0000 (18:46 -0700)
commit2ed4fe4932d78f07a4c7a0a18538dc162d8f9997
treea155d1f69f7aaeee5c21ad2707d76cbde94a4ab6
parentd95a4cfcd3cb148ef6313236fb858c81c996344f
Adding tests and fixing codegen for the Arm 'Aes' and 'ArmBase' hwintrinsics (dotnet/coreclr#27151)

* Adding arm hwintrinsic tests for AdvSimd.LoadVector64 and AdvSimd.LoadVector128

* Adding arm hwintrinsic tests for Aes.Decrypt, Aes.Encrypt, Aes.InverseMixColumns, and Aes.MixColumns

* Fixing compSetProcessor to support the Arm AES instruction set

* Adding arm hwintrinsic tests for ArmBase.LeadingZeroCount, ArmBase.Arm64.LeadingSignCount, and ArmBase.Arm64.LeadingZeroCount

* Improving the arm hwintrinsic test generator

* Regenerating the arm hwintrinsic tests

* Fixing the arm hwintrinsic codegen to support scalar and aes intrinsics

* Applying formatting patch.

* Don't pass in opts to INS_mov

* Ensure the arm Aes.Decrypt and Aes.Encrypt intrinsics set tgtPrefUse for op1 and mark op2 as delay free

Commit migrated from https://github.com/dotnet/coreclr/commit/643fda7fc7809f22e8cba4341f6e4c8a2507b6c6
88 files changed:
src/coreclr/src/jit/compiler.cpp
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp
src/coreclr/src/jit/hwintrinsiclistarm64.h
src/coreclr/src/jit/lsraarm64.cpp
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Abs.Vector128.Double.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64_Vector128/Abs.Double.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Abs.Vector128.UInt64.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64_Vector128/Abs.UInt64.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_r.csproj [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_ro.csproj [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Program.AdvSimd.Arm64.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64_Vector128/Program.AdvSimd.Arm64_Vector128.cs with 78% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64_Vector128/Add.Double.cs [deleted file]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Abs.Vector128.Byte.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Abs.Byte.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Abs.Vector128.Single.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Abs.Single.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Abs.Vector128.UInt16.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Abs.UInt16.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Abs.Vector128.UInt32.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Abs.UInt32.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Abs.Vector64.Byte.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Abs.Byte.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Abs.Vector64.Single.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Abs.Single.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Abs.Vector64.UInt16.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Abs.UInt16.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Abs.Vector64.UInt32.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Abs.UInt32.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsScalar.Vector64.Single.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/AbsScalar.Single.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.Byte.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.Byte.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.Int16.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.Int16.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.Int32.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.Int32.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.Int64.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.Int64.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.SByte.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.SByte.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.Single.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.Single.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.UInt16.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.UInt16.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.UInt32.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.UInt32.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector128.UInt64.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Add.UInt64.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector64.Byte.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Add.Byte.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector64.Int16.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Add.Int16.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector64.Int32.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Add.Int32.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector64.SByte.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Add.SByte.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector64.Single.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Add.Single.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector64.UInt16.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Add.UInt16.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Add.Vector64.UInt32.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Add.UInt32.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddScalar.Vector64.Single.cs [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/AddScalar.Single.cs with 97% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r.csproj [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_ro.csproj [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.Byte.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.Double.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.Int16.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.Int32.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.Int64.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.SByte.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.Single.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.UInt16.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.UInt32.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector128.UInt64.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector64.Byte.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector64.Int16.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector64.Int32.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector64.SByte.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector64.Single.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector64.UInt16.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LoadVector64.UInt32.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/AdvSimd_Vector128_r.csproj [deleted file]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/AdvSimd_Vector128_ro.csproj [deleted file]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector128/Program.AdvSimd_Vector128.cs [deleted file]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/AdvSimd_Vector64_r.csproj [deleted file]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/AdvSimd_Vector64_ro.csproj [deleted file]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd_Vector64/Program.AdvSimd_Vector64.cs [deleted file]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/Aes_r.csproj [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/Aes_ro.csproj [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/Decrypt.Vector128.Byte.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/Encrypt.Vector128.Byte.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/InverseMixColumns.Vector128.Byte.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/MixColumns.Vector128.Byte.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/Program.Aes.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/ArmBase.Arm64_r.csproj [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/ArmBase.Arm64_ro.csproj [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/LeadingSignCount.Int32.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/LeadingSignCount.Int64.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/LeadingZeroCount.Int64.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/LeadingZeroCount.UInt64.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/Program.ArmBase.Arm64.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase/ArmBase_r.csproj [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64_Vector128/AdvSimd.Arm64_Vector128_r.csproj with 68% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase/ArmBase_ro.csproj [moved from src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64_Vector128/AdvSimd.Arm64_Vector128_ro.csproj with 69% similarity]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase/LeadingZeroCount.Int32.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase/LeadingZeroCount.UInt32.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase/Program.ArmBase.cs [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/AesBinOpTest.template [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/AesUnOpTest.template [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/GenerateTests.csx
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/LoadUnOpTest.template [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/ScalarUnOpTest.template [new file with mode: 0644]
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/_BinaryOpTestTemplate.template
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/_UnaryOpTestTemplate.template