[RISC-V][HWASAN] Enable HWASAN for RISC-V architecture

[RISC-V][HWASAN] Enable HWASAN for RISC-V architecture

Reviewed by: vitalybuka, kito-cheng

These changes will allow to use HWASAN with RISCV64 architecture.

The majority of existing tests are passing with a few exceptions(see below).
The tests were running on QEMU, since currently there're no hardware with support
for J-extension.

For this feature to work the system must support PR_{SET,GET}_TAGGED_ADDR_CTRL
syscall. For now this is only available for a patched Linux kernel and QEMU with
enabled experimental J-extension.

Results of running HWASAN lit tests for RISC-V:
```
  Unsupported      :  6
  Passed           : 79
  Expectedly Failed:  2
```

Tests are marked as expected to fail or unsupported either because of:
- android platform not being supported
- no support for legacy hwasan v1 mode
- test config explicitly uses aarch64 option
```
UNSUPPORTED: HWAddressSanitizer-riscv64 :: TestCases/abort-message-android.cpp
UNSUPPORTED: HWAddressSanitizer-riscv64 :: TestCases/cfi.cpp
UNSUPPORTED: HWAddressSanitizer-riscv64 :: TestCases/lto.c
UNSUPPORTED: HWAddressSanitizer-riscv64 :: TestCases/print-memory-usage-android.c
UNSUPPORTED: HWAddressSanitizer-riscv64 :: TestCases/register-dump-read.c
UNSUPPORTED: HWAddressSanitizer-riscv64 :: TestCases/try-catch.cpp
XFAIL: HWAddressSanitizer-riscv64 :: TestCases/stack-oob.c
XFAIL: HWAddressSanitizer-riscv64 :: TestCases/exported-tagged-global.c
```

Differential Revision: https://reviews.llvm.org/D131345