[AMDGPU] SIFixSGPRCopies reworking to use one pass over the MIR for analysis and...
authorAlexander Timofeev <alexander.timofeev@amd.com>
Wed, 7 Sep 2022 14:14:38 +0000 (16:14 +0200)
committerAlexander Timofeev <alexander.timofeev@amd.com>
Mon, 19 Sep 2022 21:31:45 +0000 (23:31 +0200)
commit2e8817b90a9aa38c681ca1bb9075f9e8eed3f6e8
tree21ed3707da67003f350c1de72d2095b85a26a375
parent0cec96ab250e59e666d225a3b47ddd6289a82339
[AMDGPU] SIFixSGPRCopies reworking to use one pass over the MIR for analysis and lowering.

This change finalizes the series of patches aiming to replace the old strategy of VGPR to SGPR copy lowering.

  # Following the https://reviews.llvm.org/D128252 and https://reviews.llvm.org/D130367 code parts that are no longer used were removed.
  # The first pass over the MachineFunctoin collects all the necessary information.
  # Lowering is done in 3 phases:
     - VGPR to SGPR copies analysis  lowering
     - REG_SEQUENCE, PHIs, and SGPR to VGPR copies lowering
     - SCC copies lowering is done in a separate pass over the Machine Function

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D131246
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll