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intel/eu: SVB writes only happen on Gen6
authorJason Ekstrand <jason.ekstrand@intel.com>
Fri, 5 Feb 2021 14:09:47 +0000 (08:09 -0600)
committerMarge Bot <eric+marge@anholt.net>
Sun, 2 May 2021 20:20:06 +0000 (20:20 +0000)
commit2e7656ae2fdd0cd898812b5762138c14149cb6e9
tree62a52803efed0cf1ffbef05354a9ec8d738b0dc0tree | snapshot
parent0421690f83741c2214680879bbf565cd2a12ae99commit | diff
intel/eu: SVB writes only happen on Gen6

It's a Gen6 XFB thing.  It's never used for anything else so there's no
point in having a target cache switch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
src/intel/compiler/brw_eu_emit.c diff | blob | history
Domain: Graphics System / GL;