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(parent: ac935a8) | patch
drm/i915: Implement chv display PHY lane stagger setup
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 10 Apr 2015 15:21:27 +0000 (18:21 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 May 2015 13:55:22 +0000 (15:55 +0200)
commit2e523e98bb593950de2c749d4ceb45cc20313c1a
tree7e6263ccf6e240558843bcc88df1d09eafeeccadtree | snapshot
parentac935a8b6db00079e2de65cadf4c735ed8f0175bcommit | diff
drm/i915: Implement chv display PHY lane stagger setup

Set up the chv display PHY lane stagger registers according to
"Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY" v1.04

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
drivers/gpu/drm/i915/intel_dp.c diff | blob | history
drivers/gpu/drm/i915/intel_hdmi.c diff | blob | history
Domain: System / Kernel;