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[AArch64][SME2] Remove vector constraints from zip/uzp (2-vector) instruction classes
authorDavid Sherwood <david.sherwood@arm.com>
Fri, 18 Nov 2022 13:07:35 +0000 (13:07 +0000)
committerDavid Sherwood <david.sherwood@arm.com>
Fri, 18 Nov 2022 14:30:48 +0000 (14:30 +0000)
commit2e02f007a27310abaea60f7749093c95e61c813a
tree1b8712e10dd0459425dfd7060176783c41986af4tree | snapshot
parentbc270f9ed1c86db3f3a537dc6f91cda94737b915commit | diff
[AArch64][SME2] Remove vector constraints from zip/uzp (2-vector) instruction classes

The zip/uzp (2-vector) instruction classes have the incorrect
register constraints and mark the destination as also being an
input. However, the instructions are fully destructive so I've
restructured the classes.

Differential Revision: https://reviews.llvm.org/D138288
llvm/lib/Target/AArch64/SMEInstrFormats.td diff | blob | history
Domain: System / Toolchain;